In the continuing drive to reduce power requirements for electronic devices, attempts have been made to reduce power by use of low operating voltages. In certain types of circuits known as “near threshold” circuits, the supply voltage is maintained at a level only slightly above the “threshold voltage”, the point where a transistor begins to start conducting current. In other circuits known as “sub threshold” circuits the supply voltage is maintained at a level below the threshold voltage. For many circuit implementations, the most energy efficient operation occurs when the supply voltage is just slightly higher than the threshold voltage (near threshold) or below the threshold voltage (sub-threshold). A supply voltage that is substantially higher than the threshold can result in increased speed and reduced errors, but has substantial power costs.
Power efficient operation of memory array circuits is of particular importance because of their large per die transistor count and consequent large power usage. For example, static random access memory (SRAM) is commonly used as part of integrated circuit designs. As process technology has scaled it can become difficult to maintain high SRAM yields since they can be more vulnerable to process variations. For example, in scaled process technologies it can become increasingly difficult to control the variation of transistor parameters because of a variety of factors, including, for example, Random Dopant Fluctuation (RDF). Other reasons for this variation include dopant scattering effect, such as the well proximity effect, that makes the placement of dopants in metal-oxide-semiconductor field effect transistors (MOSFETs) increasingly difficult as transistor size is reduced. Transistor variability arising from dopant effects worsens as transistors are reduced in size, with each misplaced dopant atom having a greater relative effect on transistor properties, as a result of the overall reduction in the number of dopant atoms.
Such random variations between neighboring MOSFETs can have a significant impact on the read and write margins of the SRAM cell. To maintain read robustness for the cell, an eight transistor (8-T) SRAM design can be used, which can be independently optimized for read and write operations since there are separate ports for each operation. Using an 8-T SRAM cell can also lower the minimum operating voltage of the SRAM, to result in lower SRAM power consumption.
However, SRAM cells operating at low voltages can have increased susceptibility to soft errors. Soft errors are faults induced by an ionizing radiation particle strike that upsets internal data states of the SRAM cell while the circuit itself is undamaged. Even though it is unpredictable, soft error susceptibility can be a significant reliability problem for SRAM cells. Typically, SRAM designs use parity checking for single bit soft error detection, or parity based Single Error Correction/Double Error Detection (SEC-DED) codes to fix single bit soft errors. However, the probability of multi-bit soft errors increases as process technology is scaled. If all the bits in a single data word of the SRAM are physically located next to each other, a multi-bit soft error can result in multiple bits of the same word being corrupted. Such errors cannot be fixed with SEC-DED error correction codes. Other codes, e.g., BCH codes providing DEC-TED capability can also be used but are more complicated, and codes with greater robustness can be too complicated for use with low-latency SRAM access.
One of the methods to avoid single word multi-bit soft errors is to interleave bits, such that bits of the same data word are not physically adjacent. Bit interleaving can improve robustness as to soft errors because a multi-bit soft error can then manifest as single bit errors for multiple words. Therefore, for a bit interleaved SRAM the multi-bit soft error can be fixed with SEC-DED error correction codes since each corrupted word is likely to have only a single upset bit.
Although bit interleaving is effective in avoiding single word multi-bit soft errors, it also results in a “half select” disturb problem. The half select disturb problem arises from the fact that, during a write operation for a bit interleaved SRAM, a write word line for physically adjacent interleaved SRAM cells that belong to different logical words is enabled. Thus, SRAM cells (in columns) that belong to those logical words for which a write operation is not being performed, can have an active write word line while their write bit lines are unselected (generally floated after being precharged to the high supply voltage). Cells having an enabled write word line and unselected write bit lines are thus referred to as half selected cells, in that these cells are reading while the intended SRAM cells in other columns are writing. The half select disturb problem can arise in bit interleaved SRAMs using any suitable SRAM cell, including six-transistor (6-T) and 8-T SRAM cells. However, the half select disturb problem can have a significant impact on the robustness of 8-T SRAMs since it results in the half selected cells being read out on the write bit lines, and conventional 8-T SRAM cells are typically not designed to be stable under these conditions (the read and write ports in a 8-T SRAM cell are separated, and the number of transistors in the cell is increased from 6 to 8 at least in part to allow lower voltage operation by separating the read and write ports). By contrast, conventional 6-T SRAM cells are optimized to allow the same port to be used for both read and write operations, and therefore, the half select disturb problem may not impact these cells as severely as conventional 8-T SRAM cells. Therefore, 8-T SRAM cells have typically not been used to implement bit-interleaved SRAMs, and therefore, they have typically been used for applications that do not have high reliability requirements and do not use bit interleaving.